IIT Delhi Demonstrates India's First Indigenous Micro-GPU on FPGA Platform

Synopsis

Scientists at IIT Delhi have created India's first working, indigenous designed micro-GPU. The programmable graphics engine is targeted at embedded applications like e-rickshaw dashboards and industrial displays and has been demonstrated on a Spartan-7 FPGA. The team has now launched an 8–16 core version and is also working towards a silicon proof of concept for 65nm silicon, which are all currently imported to India, officials state.

The Indian Institute of Technology, Delhi has designed the “indigenous micro-GPU” which officials say can significantly lessen the country's imports dependence, for the first time in the country, researchers have created a working and demonstrable micro-GPU. All GPUs are imported now, officials said Thursday.

This work is from Electrical Engineering department. Prof. Kaushik Saha's group showed that a custom FPGA platform with a FPGA based graphics rendering engine implemented in RTL can be programmed to render graphics. The design is scalable graphics-processor “IP”—a blueprint of a piece of hardware that can be reused. It can be implemented on a silicon ASIC or programmable silicon (FPGA) device.

A compact yet truly programmable graphics-processing architecture. The goal was to achieve, as per the joint statement from researchers Akash and Ravi Teja.

Such indigenous systems may help in providing affordable platforms for digital access and they are hoping for that to come, they say. Architecture is appropriate for industrial control displays and low-cost, human machine interface (HMI) applications, said MTech student Nammi Akash.

Where it could be used

Examples of applications listed are: E-Rickshaw dashboard navigators, Inland-water navigation terminals for small fishing boats, and educational E-book readers. These are embedded systems, which are those that carry out a specific task, or process, rather than general computing. That's different from the data-centre accelerators that are common in AI workloads, although officials said GPUs are applied to AI and machine-learning engines.

The roadmap: FPGA to silicon

The prototype is an intermediate step. The researchers are working on an 8-16 core vector-style graphics processor with an optimised compiler and graphics software toolchain. They also have a plan to migrate to a PoC that will be a 65nm ASIC process node.

Why an older node

The manufacturing process is 65 nm, well down the road. The team feels these nodes could render cost-effective, silicon-based graphics useful and practical for embedded systems. The reason is that the older nodes are typically cheaper to access, although the reports examined don't provide cost data.

An academic project that aims to have industrial applications

The project allows students to weave together the arithmetic hardware, programmable architectures, compilers and embedded systems in a single environment while tackling the more fundamental issue of making systems more accessible, Prof. Saha said. Prof. Jayadeva, also from the department, said the work showcased the learning and research opportunities such initiatives can provide. The researchers also appreciated the academic environment and technical platform provided by the institute.

Context: India's indigenization drive for silicon

The project is in addition to other indigenous efforts. In February 2025, IIT Madras and ISRO announced the development of an indigenous microprocessor designed for space applications, which is based on the SHAKTI processor baseline. SHAKTI is based on the open-source RISC-V instruction set and supported by the Ministry of Electronics and Information Technology, under the Digital India RISC-V initiative.

IIT Madras Director V Kamakoti said at the time that the work formed part of the effort to indigenise semiconductors used by ISRO.

What remains unresolved

The reports are specific on what is demonstrated: An FPGA-based demonstration. The ASIC stage is not a final milestone; it's a roadmap. The reviewed reports provide no information on the commercial partner, the funding time and fabrication time. There also are no independent measures of performance included in the material reviewed.

The institute and officials quoted by the Press Trust of India have the benefit of being "first" for now. The next logical and measurable step is the multi-core design and the silicon proof of concept, to ensure that a classroom scale architecture can go to a fabrication line.